The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including an improved gate spacer and a method of manufacturing the same.
Semiconductor devices, such as dynamic random access memory (DRAM) devices, include a cell region and a peripheral region. The peripheral region includes complementary metal oxide semiconductor (CMOS) transistors. In a typical CMOS transistor, a PMOS transistor has a buried channel structure. As the integration degree of the device increases, the channel length is reduced and therefore, leakage current characteristics are degraded by applying a high electric field. Recently, a dual gate structure has been introduced to embody a PMOS transistor that has a surface channel structure. The dual gate structure represents a structure in which a p-type gate for implanting a p-type impurity is disposed in a region where a PMOS transistor is to be formed, and an N-type gate for implanting an N-type impurity is disposed in a region where an NMOS transistor is to be formed.
Meanwhile, various methods for reducing the area of a cell region of a semiconductor memory device have been suggested. One such method uses a recess gate instead of a planar gate. A recess gate is made by forming a recess in a semiconductor substrate and forming a gate in the recess to form a channel along a curved surface of the recess. Another method using a buried gate, which is formed by completely burying a gate in a recess, has also been introduced.
The buried gate is formed to be completely buried within a semiconductor substrate, thereby having an upper surface level equal to or less than a surface of the semiconductor substrate. Therefore, the buried gate structure can maintain channel length and channel width and can reduce the parasitic capacitance generated between a gate (a word line) and a bit line by 50% as compared with the prior art.
However, in configurations of a cell region and a peripheral region with the buried gate, a space (a height) of the cell region, which is corresponds to a height of a gate formed in the peripheral region, is available. To use the available space, a method of forming a bit line of the cell region when the gate is formed in the peripheral region has been introduced. Herein, the bit line is referred to as a gate bit line (GBL).